1. Field of the Invention
This invention relates to methods to self-synchronize clocks on multiple chips in a system
2. Description of Background
In a synchronous digital system comprised of multiple chips with synchronous communications among them, cross-chip functions often require a synchronized “time-zero” over a certain predefined number of clock cycles. To properly synchronize the time-zero of all the chips in the same system, a method is required to synchronize the counters that keep track of the “time-zero” on all the chips. One way to accomplish this is through the methods described in patent application Ser. No. 11/056,767, Methods to Self-synchronize Clocks on Multiple Chips in a System. All of the synchronization methods described therein rely on a synchronization signal generated off of the input reference clock and a PLL-generated global clock of the chip. This is as shown in the example in FIG. 1. These signals include a reference clock signal clkref 11, a chip global clock signal, clkg 13 and a synchronization signal 15.